Designing a high speed-low power carry select adder circuit using carbon nano tubes based on field effect transistors

Y. W. Chang, C. Y. Cheng *

Department of Electrical Engineering, College of Electrical Engineering and Computer Science, National Taiwan University, Taipei, Taiwan


The purpose of this study is designing a carry select adder using carbon nano tubes based field effect transistors. As the main focus of VLSI circuit design is designing low power and high speed circuits, various methods have been introduced and developed to obtain this goal. In this study power consumption is reduced as much as possible utilizing nano scale transistors and decreasing supply voltage. To evaluate the proposed method CSA full adder is implemented as a case study. Considering different technologies CNTFET is selected for our design due to its advantages over its counterparts. Simulations are performed in HSPICE environment. Simulation results revealed that the proposed method is able to significantly decrease power, delay and power delay production.


Full adder, CNTFET, Power consumption, Delay, Power delay product

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Article history

Received 5 November 2018, Received in revised form 10 January 2019, Accepted 20 January 2019

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Chang YW and Cheng CY (2019). Designing a high speed-low power carry select adder circuit using carbon nano tubes based on field effect transistors. Annals of Electrical and Electronic Engineering, 2(2): 1-5

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